Disclosed is a formation method for a multi-threshold-voltage fin type transistor. The formation method comprises the steps of providing a substrate which comprises a first N type threshold value region, a second N type threshold value region, a first P type threshold value region and a second P type threshold value region, wherein fin parts are arranged on the surface of the substrate; forming an isolation layer on the surface of the substrate; forming a dielectric layer on the isolation layer and the surfaces of the fin parts, wherein a first trench, a second trench, a third trench and a fourth trench are formed in the dielectric layer; forming a gate dielectric layer at the bottoms of the first trench, the second trench, the third trench and the fourth trench; forming a first P type work function layer in the third trench; forming a second P type work function layer on the surface of the first P type work function layer and in the first trench, the second trench and the fourth trench; forming a first N type work function layer on the second P type work function layer in the first trench; and forming a second N type work function layer on the surface of the first N type work function layer and in the second trench, the third trench and the fourth trench. The formation method for the multi-threshold-voltage fin type transistor is simple.