The invention discloses an EBR1553 bus protocol implementation device based on FPGA. The device comprises a host interface module, a BM recording module, a scheduling module, a message sending controlmodule, a message processing module, a logic line concentration control module, a coding module and a decoding module. The modules completely use internal logic of the FPGA to achieve a protocol stack with BC, 31 RT and BM functions which are specified by EBR1553 and can be integrated. According to the device provided by the invention, the multifunctional EBR1553 protocol stack can be achieved byusing the FPGA, and thus simulation and test costs and complexities can be reduced.