The invention discloses a 3D memory structure. The 3D memory structure comprises a plurality of partitions; each partition comprises a peripheral device layer, a contact connection layer and an arraydevice layer; and the peripheral device layer, the contact connection layer and the array device layer are stacked in sequence. By establishing a proper word line and bit line contact solution and byreasonably arranging the position of a circuit assembly of periphery under cell, the chip integration degree is improved, the CMOS chip position layout is improved, and the size of each chip is reduced.