The invention relates to a power harmonic detection system. The system comprises a sampling circuit and an FPGA (field programmable gate array). The sampling circuit comprises an A/D conversion circuit (A), a mutual inductor (B), a filter circuit and a phase-locked frequency doubling circuit (C). The FPGA comprises a control unit (D), an FFT module (E), an FIFO module (F) and a clock (G). Furthermore, a to-be-measured signal is converted into a low-voltage signal through the mutual inductor (B) and the filter circuit. After that, the converted low-voltage signal enters the A/D conversion circuit (A). Meanwhile, the low-voltage signal, converted through the phase-locked frequency doubling circuit (C), the mutual inductor (B) and the filter circuit, changes in frequency. By adopting the FPGA, the brand-new design of the power harmonic detection system is carried out. The workload can be greatly reduced by means of a DSP and the parallel operation is performed by the FPGA. Therefore, theworking efficiency is improved, and the development period is shortened.