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发明公开
CN107809242A 控制接口转换装置的倍频模块 无效 - 撤回

控制接口转换装置的倍频模块
摘要：
本发明公开了控制接口转换装置的倍频模块，包括锁相环U1、计数器U2、计数器U3、电容C1、电容C2、电容C6、电容C7、电容C8、电容C11、电容C12、电容VC1、电位器RW2、三极管Q1、电阻R3、电阻R4、电阻R5、电阻R6、电阻R7、电阻R8、电阻R9，所述锁相环U1采用NE564，计数器U2、计数器U3均采用74LS393；锁相环U1的12引脚与13引脚之间并联有电容C12和电容VC1；所述电容C6一端为信号输入端，其另一端连接锁相环U1的5引脚；所述锁相环U1的3引脚连接计数器U2的3引脚，计数器U2的1引脚连接计数器U3的6引脚，技术其U2的2引脚连接计数器U3的2引脚。本发明运用锁相环来跟踪锁定频率，并消除之间的频率误差，达到一种稳定值，从而提高了倍频电路信号的稳定性。
摘要（英）：

The invention discloses a frequency multiplier module for a control interface conversion device. The frequency multiplier module comprises a phase-locked loop U1, a counter U2, a counter U3, a capacitor C1, a capacitor C2, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C11, a capacitor VC1, a potentiometer RW2, a triode Q1, a resistor R3, a resistor R4, a resistor R5, a resistor R6, aresistor R7, a resistor R8 and a resistor R9. The phase-locked loop U1 is NE564. The counter U2 and the counter U4 are 74LS393. The capacitor C12 and the capacitor VC1 are connected between a 12th pin and a 13th pin of the phase-locked loop U1 in parallel. One end of the capacitor C6 is a signal input end and the other end is connected with a 5th pin of the phase-locked loop U1. A third pin of the phase-locked loop U1 is connected with the third pin of the counter U2. A first pin of the counter U2 is connected with a 6th pin of the counter U3. A second pin of the counter U2 is connected withthe second pin of the counter U3. According to the frequency multiplier module, a locking frequency is tracked through utilization of the phase-locked loop and a frequency error is eliminated, so a stable value is achieved, and the signal stability of a frequency multiplier circuit is improved.

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