利索-全球专利检索

  1. 登录
  2. 注册
发明公开
CN108027641A 用于在经暴露高速缓冲存储器停止运作时有效的时钟调整的方法及设备 无效 - 撤回

用于在经暴露高速缓冲存储器停止运作时有效的时钟调整的方法及设备
摘要：
响应于因高速缓冲存储器未命中所致的分派停止运作，降低处理器的时钟频率。在实施例中，倘若引发末级高速缓冲存储器未命中的加载指令为最旧加载指令及其中存在分派停止运作的连续处理器循环的数目超出阈值，且倘若自从末级高速缓冲存储器未命中以来的处理器循环的总数目不超过某一指定数目，那么针对所述加载指令降低所述处理器时钟频率。
摘要（英）：

The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a lastlevel cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and providedthat the total number of processor cycles since the last level cache miss does not exceed some specified number.

0/0