The invention discloses a high-speed frequency divider. The high-speed frequency divider comprises a subtraction circuit, an inverting circuit and an adding circuit, wherein the subtraction circuit isused for receiving a N-bit frequency division ratio signal and an input clock signal, and providing a subtraction signal; the inverting circuit is used for receiving the subtraction signal and providing an anti-reflection signal; and the adding circuit is used for receiving a high (N-1) bit of the anti-reflection signal and the frequency division ratio signal, and providing a carry signal. In thecase of even frequency division, the high-speed frequency divider can obtain a carry signal with a duty ratio of 50 percent as a frequency division signal, thereby avoiding frequency jitter. In the case of odd frequency division, the carry signal is compensated or adjusted, so that a frequency division signal with a duty ratio of 50 percent can also be obtained.