A semiconductor memory device includes first and second memory cells, first and second select transistors having first ends connected to the first and second memory cells, respectively, first and second bit lines connected to second ends of the first and second select transistors, respectively, and a select gate line connected to the first and second select transistors. A write operation includes first and second program loops. While a program pulse is being applied to a word line, a first voltage is applied to the first bit line, a second voltage to the second bit line, and a third voltage to the select gate line. Before the program pulse is applied to the word line, the second voltage is applied to the second bit line and a fourth voltage is applied to the select gate line for different time periods while in the first and second program loops, respectively.