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发明公开
CN108365843A 集成电路和电子设备 无效 - 撤回

集成电路和电子设备
摘要：
本发明涉及集成电路。提供能够抑制逻辑块间的信号延迟的集成电路。集成电路具备：分别具有第一逻辑块和包含第一开关电路的第一开关块的第一至第三基本单元；第一布线，将第一基本单元的第一开关电路和第一逻辑块连接；第二布线，将第一基本单元的第一开关电路和第二基本单元的第一开关电路连接；第三布线，将第一基本单元的第一开关电路和第三基本单元的第一开关电路直接连接；第四布线，将第二基本单元的第一开关电路和第一逻辑块连接；第五布线，将第二基本单元的第一开关电路和第三基本单元的第一开关电路连接；以及第六布线，将第三基本单元的第一开关电路和第一逻辑块连接，第三布线与第二基本单元的第一开关电路的输入端子之一连接。
摘要（英）：

An integrated circuit according to an embodiment includes: first through third basic tiles, the second basic tile being located between the first basic tile and the third basic tile, each of the basic tiles including a first logic block configured to perform a logical operation and a first switch block, the first switch block including a first switch circuit, the first switch circuit including: two-terminal switch elements arranged in a matrix form; input terminals, each of the input terminals being connected to one of terminals of each of the two-terminal switch elements aligned in the same column; and output terminals, each of the output terminals being connected to the other one of the terminals of each of the two-terminal switch elements aligned in the same row.

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