The invention discloses a logic verification method and device which are applied to a base station logic verification platform. Testbench obtains a parameter text required for executing correspondinglogical implementation functions in a DUT, generates an input stimulus according to the parameter text, calls a signal line which transmits the input stimulus in a bus interface, transmits the input stimulus to the DUT, calls a signal line which transmits a logic verification result in the bus interface, obtains the logic verification result of the logic verification by the DUT based on the inputstimulus, and carries out logic verification on the corresponding logic implementation functions in the DUT based on the logic verification result. When the logic verification of the different logic implementation functions in the DUT is carried out, the logic verification is achieved directly by calling the signal line transmitting the input stimulus in the bus interface which means that the signal line can be directly changed in the bus interface, the change of the internal code of the Testbench is not needed, and the efficiency of the logic verification is improved.