The invention provides a virtual impedance design method in a parallel system. The method comprises the steps of 1, analyzing the impedance of an inverter in the parallel system, wherein the obtainedimpedance of the inverter in the parallel system is resistive impedance; step 2, according to the fact that the impedance of the inverter in the parallel system is resistive impedance, calculating andobtaining an output reference voltage amplitude value Eref of the inverter through a resistive droop method; step 3, introducing a virtual impedance Zv(s), and based on the output reference voltage amplitude value Eref of the inverter and the virtual impedance Zv(s), calculating and obtaining a closed-loop control voltage reference Vref; and step 4, performing coordinate transformation on the closed-loop control voltage reference Vref obtained in the step 3 to obtain a formula which is as shown in the specification in a two-phase rotating coordinate system. According to the method, by increasing the virtual impedance between the inverters to balance the harmonic power, the harmonic current is reduced. In a distributed power supply system, a UPS system and a railway train parallel auxiliary system, the virtual impedance method designed in the invention can balance the harmonic current in the parallel system, so that the reliability and the stability of the parallel system are greatly improved.