The invention discloses an edge computing hardware architecture based on RISC-V. The edge computing hardware architecture comprises an edge computing controller based on an RISC-V instruction set, used for controlling a CNN hardware accelerator and processing the operation result of the CNN hardware accelerator; a communication protocol interface, realizing data communication between a RISC-V-based controller and a CNN hardware accelerator; and a CNN hardware accelerator used for carrying out convolution processing on the data in the specified memory and sending a result obtained after operation of the CNN accelerator to the controller. With the help of characteristics of free opening, concise and modular of the RISC-V instruction set, the edge computing hardware architecture solves problem of high requirements on low power consumption, low area and low cost of equipment on a edge computing end. Meanwhile, due to the fact that the RISC-V instruction set has independent expansibility and good backward compatibility, the processor designed on the basis of the RISC-V instruction set is applied to a mobile edge device end, and the problem that a traditional MCU cannot carry out lightweight artificial intelligence processing due to programming limitation can be solved.