The invention discloses a device and method for reducing the sampling rate of an ADC. The device comprises an IQ modulator, a single-pole double-throw switch, a medium frequency band-pass sampling link, a PLL reference clock configurator and a zero intermediate frequency sampling link, wherein the intermediate frequency band-pass sampling link and the zero intermediate frequency sampling link arearranged in parallel, and the single-pole double-throw switch is used for controlling the opening and closing of the intermediate frequency band-pass sampling link and the zero intermediate frequencysampling link and selecting different sampling modes. According to the invention, a traditional zero-intermediate frequency low-pass sampling device and a band-pass sampling device are combined; the built-in switch is used for channel selection; when the signal center frequency is low, a low-pass sampling device is adopted; when the signal center frequency is high, the band-pass sampling device isadopted, the structure is simple, machining is convenient, mass production can be achieved, the structure limitation is small, implementation is easy, the design method is more flexible, signal receiving of different frequency bands can be achieved by adjusting channel selection, the circuit design from the intermediate frequency to the base band is simplified, and the sampling rate of an ADC isreduced.