The invention discloses a Cache system verification method of a multi-core RISC-V processor, and relates to the field of simulation verification algorithms. The method aims at solving the problems that Cache verification is difficult to expand, excitation space is redundant and non-uniform coverage exists in Cache system simulation verification random excitation in a multi-core RISC-V processor inthe prior art. The invention provides a Cache system verification method for a multi-core RISC-V processor. The method comprises the following steps: firstly, establishing a directed bipartite graph-based Cache system abstract model in the multi-core RISC-V processor; converting an original disordered Cache excitation space of the RISC-V processor into four layers of ordered tree-shaped spaces byadopting a hierarchical equivalence class partitioning algorithm; traversing the leaf node set of the excitation space tree by adopting a breadth-first algorithm to obtain a non-redundancy full-coverage leaf node sequence containing high-level excitation information; and finally, converting each leaf node into a test instruction of the RISC-V core through a riscv conversion function related to the RISC-V. According to the method and the device, non-redundancy uniform coverage of the excitation space can be realized on the basis of ensuring the verification coverage rate.