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发明授权
CN1130646C 微处理机2倍核单元设计 失效 - 权利终止 复审申请

微处理机2倍核单元设计
摘要：
一微处理机能有选择地以总线的速度，或者以数倍总线的速度操作。此微处理机包含有一锁相回路，以产生微处理机内部操作用的时钟信号和总线上传送数据操作用的总线时钟信号。本发明使得微处理机磁心能以与地址/数据总线相同的频率或者为其二倍的频率运行。
摘要（英）：

A microprocessor that operates at the speed of the bus or at a speed which is a multiple of the bus speed on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals to clock the operations within the microprocessor and bus clock signals to clock data transfer operations between the microprocessor and the bus.

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