A technique implements a novel high-speed high-density packet buffer utilizing a combination of high-speed and low-speed memory devices. The novel packet buffer is organized as a plurality of FIFO queues where each FIFO queue is associated with a particular input or output line. Each queue comprises a high- speed cache portion that resides in high-speed memory and a low-speed high- density portionthat resides in low-speed high-density memory. The high-speed cache portion contains FIFO data that contains head and/or tail associated with the novel FIFO queue. The low-speed high-density portioncontains FIFO data that is not contained in the high-speed cache portion.