A digital signal processing part (103) has a reconfigurable device (131), which uses programming data to configure a decoding part (133) and an encoding part (134). The decoding part (133) is synchronized with the signal outputted from a receiving part (121) and performs signal demodulating and decoding processes. A CPU (105) downloads programming data of a different radio communication format and stores the downloaded data into a memory part (106) via a general-purpose bus (104). The CPU (105) further reads the programming data stored, and reconfigures the reconfigurable device (131). The memory part (106) stores the programming data.