The system for recovery from disaster includes at least clock source to provide the hardware watch dog with clock signal, memory for storing important information of the main control unit regularly, main control unit and hardware watch dog counter of FPGA or CPLD. The hardware watch dog counter executes the monitoring of the main control unit, and in case of failed main control unit, the hardware watch dog counter will overflow to trigger the reset signal of the main control unit so as to make the main control unit re-start, read maintained information from the memory and recover from disaster. The present invention also discloses the method of recovering from disaster based on the said method. The present invention can strength the stability, reliability and antijamming capability of the main control unit obviously, and raise the self-healing capacity of the main control unit.