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Invention Grant
CN1741387B 锁存反向电路与使用其的触发器与双锁存数据触发器 失效 - 权利终止

锁存反向电路与使用其的触发器与双锁存数据触发器
Abstract:
一种锁存反向电路与使用该锁存反向电路的触发器与双锁存数据触发器。锁存反向电路包含一第一PMOS晶体管、一第二PMOS晶体管、一第一NMOS晶体管、一第二NMOS晶体管、一第一电平调整单元、以及一第二电平调整单元。该锁存锁存反向电路利用第一电平调整单元与第二电平调整单元事先调整第二PMOS晶体管的源极与第二NMOS晶体管的漏极的电平，藉以提升锁存反向电路的反应速度。
Abstract(English):

A latch reverse circuit consists of the first PMOS transistor , the second PMOS transistor , the first NMOS transistor , the second NMOS transistor , the first level regulation unit and the second level regulation unit . It features that the first level regulation unit and the second level regulation unit are used to regulate levels of source electrode of the second PMOS transistor and drain electrode of the second NMOS transistor in advance for rising reaction speed of latch reverse circuit .

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