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发明公开
CN1771561A 比特同步检测装置 无效 - 撤回

比特同步检测装置
摘要：
一种用于检测信号中的信息的检测装置，包括：用于在时间将信号积分的积分装置，以使得积分装置在大约周期时间间隔的开始时间基准上被周期地复位；以及抽样与保持电路，用于在大约周期时间间隔的结束时间基准上周期地抽样和保持积分信号(int)，并从而传送另一信号(fs)。检测装置还包括：信号时间延迟的链(CHDL)，该链(CHDL)的输入被耦合以接收另一信号(fs)；和组合装置(CBMNS)，具有耦合到链(CHDL)的信号抽头的组合输入，以致于组合输入的数量和将组合输入耦合到链(CHDL)的信号抽头的位置对应于信号中的信息。
摘要（英）：

Detection means for detecting information in a signal, comprising integration means for integrating the signal over time such that the integration means is periodically reset at about the start time reference of a periodic time interval; and a sample&hold circuit for periodically sampling and holding the integrated signal (int) at about an end time reference of the periodic time interval and thereby delivering a further signal (fs). The detection means further comprises a chain (CHDL) of signal time delay elements, an input of the chain (CHDL) being coupled to receive the further signal (fs); and combining means (CBMNS) having combining inputs coupled to signal taps of the chain (CHDL), such that the number of the combining inputs and the position of coupling the combining inputs to the signal taps of the chain (CHDL) correspond to the information in the signal.

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