The utility model provides an FPGA-based IEC61588V2 event message detector comprising a half-byte counter controller, a destination MAC address register, a message type register, a UDP message port number register, a message transmission characteristic register, a message version register, comparers and an and-gate circuit. The half-byte counter controller distributes network frame fields to corresponding registers for latching; and the comparers compare the network frame fields with a given value, and comparative results generate pulse interruption request signals through the and-gate circuit. The detector works between a data link layer and a physical layer chip of an Ethernet port and is used for realizing high-accuracy detection of PTP synchronous messages of IEC 61588V2 transformer station network time and informing a CPU of generation of timestamps.