The utility model provides an FPGA (field programmable gate array) chip and BMC (baseboard management controller) chip coordinated power management system for an ATCA (advanced telecom computing architecture) blade. The system comprises an FPGA chip, a BMC chip, N power modules and a case manager, wherein enabling pins and Power Good pins of the N power modules are connected with IO (input/output) pins of the FPGA chip respectively; output ends of the N power modules are connected with AD voltage sampling interfaces of the BMC chip; the FPGA chip communicates with the BMC chip through an I2C (inter-integrated circuit) bus; and the case manager is in bidirectional connection with the BMC chip. The FPGA chip and BMC chip coordinated power management system for the ATCA blade indicates whether the FPGA chip is electrified normally or not according to the state of an LED (light-emitting diode) indicating lamp, and finding of power failures with hardware means is avoided whenever possible, so that troubleshooting is simple and efficient.