The present utility model discloses a PWM signal power-up/power-down protection circuit comprising a hysteresis comparison circuit, an AND gate circuit, a first power supply monitoring circuit, a second power supply monitoring circuit and a buffer circuit. The AND gate circuit is respectively connected with the hysteresis comparison circuit, the first power supply monitoring circuit, the second power supply monitoring circuit and the buffer circuit. According to the technical scheme of the utility model, by means of the power supply monitoring circuits and the hysteresis comparison circuit, the power supply condition of the circuit can be monitored at any time. When the circuit is powered on, the voltage is lower than a preset threshold. At this time, the output of PWM signals is limited. Meanwhile, when the circuit is powered down, a transistor is not switched on. In this way, no PWM signal is outputted through the buffer module, so that the blocking of PWM signals is realized. As a result, semiconductor devices are protected. Only when the circuit is powered on and is restricted to a certain degree at all levels, the PWM signals are unlocked. Therefore, the damage to semiconductor switching devices caused by the initial power-on or the power-down of the circuit at one level can be avoided. As a result, the service life of semiconductor switching devices is prolonged, and the cost of products is saved.