The utility model relates to a communication system, in particular, a radar echo signal receiving system. The radar echo signal receiving system can mainly complete the receiving of intermediate-frequency signals, and can either synchronously receive two paths of signals or acquire one path of signals so as to optimize system resource utilization. A trigger is connected with a buffer and is used for receiving rising edge trigger signals and then outputting pulse signals to an FPGA; the buffer is adopted as a temporary storage zone of input signals; the FPGA can complete the logic control of the whole system; a signal conditioning circuit is connected with an A/D conversion module; after being processed by the signal conditioning circuit, the external signals are controlled in a processable range of the A/D conversion module; a bus control chip is adopted as a bridging chip so as to transmit data between a PCI bus and a local bus; and a CPCI bus can be utilized to complete acquisition control command issuing and acquisition data uploading functions; through channel selection, and with a CPCI bus controller adopted, synchronous acquisition of I and Q signals can be realized, and alternate acquisition of one path of signals can be also completed.