The utility model relates to a seismic data compressor arrangement based on FPGA, this device break the structure of traditional signal conversion code compression, and according to compressed sensing theory, the at first sparse expression of wavelet transform for the seismic data to gathering, then the matrix is measured in the formation according to the matrix aufbau principle, utilizes the measurement matrix to be dimension reduction to sparsity coefficient at last to obtain the packed data. It is not sparse on the time territory to seismic data to and random measurement matrix hardware realizes difficult and experimental result stable problem inadequately, and this device realizes on FPGA that one -dimensional wavelet transform, chaos sequences measure the matrix and construct and vectorial reduction of dimensionality scheduling algorithm, and the realization is to seismic data's compression, the effectual seismic detector data transmission ability that has promoted. This device is when accomplishing 256 sampling points to the compression of 64 sampling points, and it is low to 0.01s to compress the used time, and the reconsitution error is less than 0.05.