The utility model discloses a processor chip simulator, include: monitoring module, treater nuclear and program memory, the monitoring module is connected with user's computer through the debugging passageway, program memory is connected with the monitoring module according to address bus through first criterion numeral, the monitoring module passes through the second criterion numeral and is connected with treater nuclear according to address bus. The utility model discloses the code that user program carried out at every turn can be taken notes and show and coverage condition is carried out.