A semiconductor memory device has memory cells 2 and decoder circuitry 3 disposed centrally thereof. A ground line 7' extends around the memory cells 2 and the decoder circuitry 3. Control circuits 41 to 46 are disposed beneath or outwardly of the ground line 7'. Signal lines 5' for connecting the control circuits to one another are disposed outwardly of the control circuits41 to46. A power line 6' is inturn disposed outwardly of the signal lines 5'. This layout can provide for a reduction in the number of bridges required.