A PCM signal processor having a signal input terminal which receives a PCM data signal from a PCM data signal reproducing apparatus such as a VTR (18R), a memory (14) for storing the PCM data signal, a standardized signal input terminal for providing a standardized signal corresponding to a synchronizing signal for synchronizing the VTR (18P), an address counter (38) for designating the address of the memory (14) which is to be read, and means for providing the address counter (38) with preset data in response to the standardized signal.