Disclosed is a dynamic-type semiconductor memory device comprising a group of sense amplifiers (SA), a plurality of pairs of bit lines (BL, BL ) extending from the sense amplifiers, and a plurality of dynamic-type memory cells (MC) connected to each bit line. Each pair of bit lines is short circuited and then precharged to a high potential level before a reading operation. A control line ( ) activating the sense amplifiers is commonly used as a control line for bringing about the precharging of each pair of bit lines, thereby assisting in attainment of high degree of integration and a high short-circuiting speed.