Analog video information from a radar antenna rotating once each 2 seconds and emitting 2000 pulses per second is digitized by an A/D converter (15) which feeds a sweep memory (16) comprising 1024 range cells each storing one pixel. The analog antenna bearing 0 is digitized by a synchro/digital converter (19) and its sine and cosine fetched from a ROM table and supplied to X and Y rate multipliers (18) whose other input is a constant frequency. The pixels in the sweep memory (16) are written to X and Y coordinate addresses, determined from their range and bearing coordinates by the rate multipliers, in an intermediate storage block memory (17). Of the 4.096.000 pixels per antenna rotation, a central processor unit (20), operating in accordance with an algorithm, writes only 1048576 final pixels, four at a time, to a radar display refresh memory (3, 21) from which these pixels, in cartesian coordinate format, are transferred in page mode through a line buffer (30) to a D/A video output unit (5) and thence to a monitor (4) which provides a raster scan display of 1024 x 1024 pixels corresponding to the PPI information produced by the antenna. In controlling the transfer of pixels from the block memory (17) to the radar display refresh memory (3, 21), the central processor unit (20) forms and uses a table of memory block addresses associated with 4096 possible antenna bearing values, each memory block occurring once only in the table.