A method for fabricating high performance NPN bipolar transistors which result in shallow, narrow base devices is described. The method includes depositing a polycrystalline silicon layer (30) over a monocrystalline silicon surface in which the base and emitter regions (42, 44) of the transistor are to be formed. Boron ions (32) are ion implanted into the polycrystalline silicon layer (30) near the interface of the polycrystalline silicon layer with the monocrystalline silicon layer. An annealing of the layer structure partially drives in the boron into the monocrystalline silicon substrate. Arsenic ions (38) are ion implanted into the polycrystalline silicon layer (30). A second annealing step is utilized to fully drive in the boron to form the base region (42) and simultaneously therewith drive in the arsenic to form the emitter region (44) of the transistor. This process involving a two-step annealing process for the boron implanting ions is necessary to create a base with sufficient width and doping to avoid punch-through. There is also described a method for forming NPN transistors in an integrated circuit.