A memory system includes an integrated circuit comprising a plurality of testably interconnectable cells (12, 16) in a tessellation on a semiconducting wafer (10). A controller (14) for acting as an interface between the wafer (10) and some host system (122) is coupled to the wafer (10) via a port (14) formed by the omission of one of the cells (12, 16) from the tessellation. Each cell (12, 16) comprises plural-bit data storage registers each having an associated single-bit access register (54) and an associated single-bit control register (56). During a growth phase a state machine (58) co-operates with global signals and test data from the controller (120) to operate data-testing and inter-register (52, 54, 56) coupling logic (50) to form a branched-labyrinth of tested cells (12, 16) characterised by rapid growth and efficient incorporation of functional cells. After growth data is transferred between the chain of data storage registers (52) and the chain of access registers (54) so formed dependently upon the contents of an associated chain of control registers (56). A rapid retrieval associative memory facility is incorporated allowing named data to be withdrawn on presentation of a maskable naming word to the control register chain.