An output buffer circuit has a data input terminal (IN) which receives logic data, load and drive transistors (20,22), a driver (24) for selectively turning on the transistors (20, 22) in accordance with the logic value of the logic data, a data output terminal (OUT) which is connected to a power source terminal (VD) of the VDD level through a current path of the load transistor (20) and is grounded through a current path of the drive transistor (22), and a capacitor (26) connected as a load to the data output terminal (OUT). The output buffer circuit further has a transition detector circuit (46) for generating a pulse signal in responseto a change in level of each of address signals (A1 - AN), and a preset circuit (48) for supplying, in response to the pulse signal, a charge or discharge current to the capacitor (26) while a voltage at the data output terminal (OUT) is not at the VDD/2 level.