As shown in Figure 2, a synchronising signal interface circuit for a television monitor comprises two exclusive-OR gates G1 and G2 which function as controllable inverters. Line and field sync. signals applied at respective inputterminals T1 and T2 are fed to signal inputs SGN1 and SGN2 of the gates G1 and G2, and integrated versions of these signals are produced by respective integrators (Rb, Rc, C) and fed to control inputs INV1 and INV2. Each of the line and field sync. signals has a duty cycle which results in the logic level (0 or 1) of the sync. pulses of the signal being opposite to the logic level (1 or 0) of the integrated version. Due to the exclusive-OR function of the gates G1 and G2, the logic level or polarity of the output sync. signal pulses will always be the same (negative), for both negative and positive polarity of the input sync. signal pulses. A gate G3 combines the output sync. signal pulses to produce a composite sync. signal.