@ The video signal processing apparatus of the present invention is comprized of a video signal dividing circuit for dividing the input video signals into N channels, and a signal combining circuit for combining these N-channel signals into the original unitary channel signals. There is disclosed an appararus for dividing video signals, wherein, in the process of dividing input video signals into N-channel signals, the input video signals are written into a memory while write address control is performed in dependence upon clock signals of the input video signals. These N-channel signals represent N signal subsections divided from a section corresponding to a predetermined unit time duration of the input video signals. Signals are read out from these subsections starting from the foremost data of each said subsection as read-out address control cycles sequentially through these subsections. N latch circuits are used for sequentially latching signals read out from the memory with the aid of N latch pulses each having a frequency equal to 1/N times the clock signal frequency and phase-shifted relative to one another by a duration equal to the clock signal period. The output signals from the N latch signals are taken as said N-channel signals. There is also disclosed a signal combining or restoration circuit, wherein, in the process of effecting image processing of said N-channel signals as required, separately compressing the processed signals along time axis and recombining the resulting signals into single-channel signals, the N-channel signals are written into the memory as control cycles sequentially through the respective channels, and the N-channel signals thus written into the memory are read out in the original signal sequence.