发明公开
- 专利标题: Inter-frame encoding/decoding equipment provided with a system for detecting a transmission error
- 专利标题(中): 设备具有用于检测传输错误的系统帧间编码/解码。
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申请号: EP84304062.7申请日: 1984-06-15
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公开(公告)号: EP0135255A2公开(公告)日: 1985-03-27
- 发明人: Kuroda, Hideo , Mukawa, Naoki , Hiraoka, Makoto , Matsuda, Kiichi , Nishiwaki, Mitsuo , Tsugane, Shuzo
- 申请人: NIPPON TELEGRAPH AND TELEPHONE CORPORATION , FUJITSU LIMITED , NEC CORPORATION
- 申请人地址: 1-6 Uchisaiwaicho 1-chome Chiyoda-ku Tokyo JP
- 专利权人: NIPPON TELEGRAPH AND TELEPHONE CORPORATION,FUJITSU LIMITED,NEC CORPORATION
- 当前专利权人: NIPPON TELEGRAPH AND TELEPHONE CORPORATION,FUJITSU LIMITED,NEC CORPORATION
- 当前专利权人地址: 1-6 Uchisaiwaicho 1-chome Chiyoda-ku Tokyo JP
- 代理机构: Billington, Lawrence Emlyn
- 优先权: JP106806/83 19830616
- 主分类号: H04N7/13
- IPC分类号: H04N7/13
摘要:
An inter-frame encoding/decoding equipment for television signals consists of inter-frame encoding equipment encoding a difference between television signals and the output of a frame memory and inter-frame decoding equipment which receives an encoded signal sent from the inter-frame encoding device via a transmission line, which decodes by adding the output of the frame memory to the encoded signal. The inter-frame encoding equipment is provided with a first operation circuit which operates the remainders obtained by dividing, by a predetermined value, the number of bits of logic "1" in the bit groups into which the output or the input of the frame memory is divided by a predetermined unit. The inter-frame decoding equipment is provided with a second operation circuit which operates the remainders obtaiend by dividing, by a predetermined value, the number of bits of logic "1" in the bit groups into which the output or the input ot the frame memory is divided by a predetermined unit. The inter-frame decoding equipment is further provided with a comparator circuit which compares and checks the values operated by the first and the second operation circuits to detect a transmission error.
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