A tag control circuit (300') in a memory access control apparatus in a digital computer system including a central processor (1) having a buffer storage (100), including a tag information store and update circuit (23, 30), and a circuit (24, 26, 27) for finding the necessity of operation for invalidation of the tag information and/or transmission of invalidation information to the central processor. The tag control circuit (300') includes a first circuit (40, 42, 43) storing a plurality of access requests of the necessity operation found at the necessity of operation-finding circuit, a second circuit (51, 52, 53) storing a plurality of invalidation execute information found at the necessity of operation-finding circuit, and a circuit (19') receiving a new access request and the access request stored in the first storing circuit and outputting one access request.
The tag control circuit (300') may further include a third circuit (45) storing only store access requests before supplying them to the necessity of operation-finding circuit, an output of which is connected to the access request receiving and outputting circuit. The access request receiving and outputting circuit may output one access request defined by the following priority order: a new read access request, an access request stored in the first storing circuit, and a store access request stored in the third storing circuit.