发明公开
- 专利标题: A memory hierarchy and its method of operation
- 专利标题(中): 存储器层级和它的操作方法。
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申请号: EP85112902.3申请日: 1985-10-11
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公开(公告)号: EP0185867A2公开(公告)日: 1986-07-02
- 发明人: Pomerene, James Herbert , Puzak, Thomas Roberts , Rechtschaffen, Rudolph Nathan , So, Kimming
- 申请人: International Business Machines Corporation
- 申请人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 代理机构: Ahlman, Bertel
- 优先权: US685527 19841224
- 主分类号: G06F12/08
- IPC分类号: G06F12/08
摘要:
A prefetching mechanism for a memory hierarchy which includes at least two levels of storage, with L1 (200) being a high-speed low-capacity memory, and L2 (300) being a low-speed high-capacity memory, with the units of L2 and L1 being blocks and sub-blocks respectively, with each block containing several sub-blocks in consecutive addresses. Each sub-block is provided an additional bit, called a r-bit, which indicates that the sub-block has been previously stored in L1 when the bit is 1, and has not been previously stored in L1 when the bit is 0. Initially when a block is loaded into L2 each of the r-bits in the sub-block are set to 0. When a sub-block is transferred from L1 to L2, its r-bit is then set to 1 in the L2 block, to indicate its previous storage in L1. When the CPU references a given sub-block which is not present in L1, and has to be fetched from L2 to L1, the remaining sub-blocks in this block having r-bits set to 1 are prefetched to L1. This prefetching of the other sub-blocks having r-bits set to 1 resufts in a more efficient utilization of the L1 storage capac- i ty and results in a higher hit ratio.
公开/授权文献
- EP0185867B1 A memory hierarchy and its method of operation 公开/授权日:1991-07-24
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