An integrated circuit includes capacitances of different capacitance values, this circuit having rows of basic capacitances, while the capacitances have different numbers of basic capacitances connected in parallel between a first connection electrode and an associated second connection electrode. Plural rows have the same number of n basic capacitances and in different ones of these rows different numbers of basic capacitances form part of the capacitances, all the remaining basic capacitances of the relevant rows being dummy capacitances. The second capacitance electrodes are connected to one or more further connection electrodes.