A gallium arsenide NAND gate (100) is connected between a power source (V DD ) and a ground potential. The gate (100) is comprised of a load transistor (20) of a normally-on type field effect transistor having an output terminal (C) and a drain connected to the power source (V DD ), a first driver transistor (22) of a normally-off type field effect transistor having a gate electrode as a first input terminal (IN,) and a source-to-drain current path series-connected to that of the load transistor (20), and a second driver transistor (24) of two normally-off type field effect transistors (24A, 248) having a common gate electrode for a second input terminal (IN 2 ) and source-to-drain current paths series-connected between the power source (V po ) and the ground potential through the series-connected first driver transistor (22) and load transitor (20). The normally-off type field effect transistors (24A, 24B) are parallel-connected to each other so as to equally constitute a single driver transistor as the second driver transistor (24).