发明公开
- 专利标题： Interleaving circuit
- 专利标题（中）： Verschachtelnde Schaltungsanordnung。
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申请号： EP86106428.5申请日： 1986-05-12
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公开(公告)号： EP0202571A2公开(公告)日： 1986-11-26
- 发明人: Takagi, Yuji , Satoh, Isao , Sugimura, Tatsuo
- 申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 申请人地址： 1006, Oaza Kadoma Kadoma-shi, Osaka-fu, 571 JP
- 专利权人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人地址： 1006, Oaza Kadoma Kadoma-shi, Osaka-fu, 571 JP
- 代理机构： Kirschner, Klaus Dieter, Dipl.-Phys.
- 优先权： JP101823/85 19850514
- 主分类号： G11B20/18
- IPC分类号： G11B20/18 ; H03M13/22 ; H03M13/00
摘要：
In the interleaving circuit, writing and reading are executed on the two dimensions array memory according to a first address sequence and a second address sequence, and product codes errors occurred on the same column are propagated to the columns which are different with each other thereby to scatter the errors to minimize the decrease of the error correction capability of the product codes.
公开/授权文献
- EP0202571B1 Interleaving circuit 公开/授权日：1992-05-13
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