Using a comparatively low supply voltage of, e.g., +5 V and a minus great voltage, the voltage difference between the gate (7) of an MNOS transistor and a P-type well region (2) in which the MNOS transistor is formed is relatively changed to execute the writing and erasing of the MNOS transistor. Thus, the potential of an N-type semiconductor substrate (1) can be fixed to a comparatively low potential, e.g., about +5 V, so that a P-channel MOSFET formed on the semiconductor substrate (1) operates with an ordinary signal level. Consequently, an EEPROM whose peripheral circuits are constructed of CMOS circuits can be provided. Accordingly, reduction in the power consumption of the EEPROM can be attained.