An interface circuit for a video signal hard copy apparatus comprises a delay circuit (7) for setting arbitrarily a delay of a sync signal, a sampling clock generation circuit (8) for producing a sampling clock signal having a predetermined phase relation with a video sync signal through the delay circuit (7) and a data sampling circuit (3) for sampling an image signal by the sampling clock signal. An image data memory (4) stores the output of the sampling circuit and a control circuit (9) receives the data of the memory circuit (4) and sets the delay of the delay circuit (7). The arrangement is such that, in operation, data samples are compared in order to set the delay.