A circuit and method for generating a read complete signal for a high speed densely packaged monolithic memory is disclosed. The memory (34) is designed to utilize and externally generated ad­dress valid signal which indicates that the address to the memory is valid. The receipt of the address valid signal sets a set/­reset latch (18) and starts the memory (34). The addressed memory cells are sensed. When at least one memory cell has data are its output below a threshold, the data are said to be un­stable and the set/reset latch is then conditioned to be reset. When the data sensed by all the sensing circuits (36) are stable, a signal (ADV) is sent to the set/reset latch (18) to cause it to be reset. The resetting of the set/reset latch (18) causes an output thereof ot change state. This state change comprises the read complete signal (RC) which is used to determine the read cycle time of the memory and may also be used in diagnostic tests of the memory.