A device having a number of general registers each allocated an input / output port and a number internal "buried" state registers. A user-controlled signal permits observation of the contents of the buried state registers at an input/output port although these registers are not allocated an input! output port. Each register is connected to a logic circuit internal to the device by a dedicated feedback path so that all registers can be used to specify states in a state machine sequencer. A fuse-programmable XOR gate permits a user to control generation of signals at the ports by permitting enabling and disabling of an inverting output buffer. Asynchronous reset and synchronous preset of the registers is prov ided. In addition to the dedicated feedback paths, programmable feedback paths are provided. An output inverter can selectably be enabled from internal signals or from an external pin. The input/output circuit can be deployed in banks, each bank selectably receiving the same or a different clock. The registers can be preloaded via an internally-generated signal or from the external pins. In an alternative embodiment, a programmable AND array and a pair of programmable OR arrays, each serving one of the banks, provides a flexible programmable logic array device with observable buried states.