提供了一种用于在具有其通过频分和抑制用于数字数据处理系统中获得的扫描信号的下降沿的数字数据信号的尾随脉冲边沿的重合的发生获得符合脉冲集成低晶体面积要求的电路装置。 的电路装置包含一个输入门，其由第一NOR门（a）和一第二或非门（b）中，第一NOR门的第二或非门（b）该采样信号的到所述第一输入，其中所述第一输入的 （a）是一个系统时钟信号（K和NOR门（A，b）是交叉耦合的经由所述第二输入。第三NOR门（c）的第一输入是（经由反相器I1）连接到第一输出NOR -Gatters（a）中，而数据信号（DE）是在第二输入直接位于和在第三NOR门（c）中的第三输入反相延迟的数据信号。

It is an integrable with low crystal area requirement circuit arrangement for obtaining a coincidence pulse when the coincidence of the trailing pulse edges of a digital data signal with the falling edges of sampling signals occur specified which are obtained by frequency division and blanking for a digital data processing system. The circuit arrangement contains an input gate which consists of a first NOR gate (a) and a second NOR gate (b), wherein the first input of the second NOR gate (b) the sampling signal, the first input of the first NOR gate (a) a system clock signal (K is and the NOR gates (a, b) are cross-coupled via the second input. the first input of a third NOR gate (c) through an inverter (I1) to the output of the first NOR -Gatters (a), while the data signal (De) is located directly at the second input and the delayed data signal inverted at the third input of the third NOR gate (c).