Voltage controlled, triggered oscillator including a NAND gate (12) and a set of series connected triggerable delay circuits (14), the output of the NAND gate (12) being fed back to one of its inputs through the delay circuits (14). A trigger signal (Vf) is applied to another input of the NAND gate (12) and to triggering inputs of the delay circuits (14). When the trigger signal is asserted, each delay circuit (14a, 14b) produces an output signal of state which tracks the state of its input signal but with a predetermined delay so that the NAND gate output oscillates with a frequency determined by the delay times of the delay circuits (14) and the propagation time of the NAND gate (12). When the trigger signal is deasserted the NAND gate output is terminated and each delay circuit (14a, 14b) drives its output signal high regardless of the state of its input signal so that the oscillator may be rapidly retriggered.