An address information line (3) of a microprocessor (1) informs a memory management unit (4) of such address infor­mation that a current address is identical to an address before one bus-cycle or two bus-cycles or is a new address. Since the address information line (3) has a light load, the address information is transmitted at high speed. In addition, if the current address is identical to the address before one or several bus-cycles, address conversion within the memory management unit (4) can be accelerated in such a way that these addresses are temporarily stored in the memory manage­ment unit (4), whereupon the corresponding address is read out.