A frequency response compensation circuit includes a first forward gain stage (J1, T1, T1ʹ, R1, R1ʹ, R3, R3ʹ) and a second reverse gain stage (J2, T2, T2ʹ, RE, REʹ, R2, R2ʹ) coupled to the first stage in negative feedback mode. The reverse gain stage depresses the gain of the first stage at low frequencies. When the frequency response of the reverse gain stage begins degrading, which corresponds to the frequency of the real zero of the compensation circuit, the gain of the compensation circuit begins increasing and increases until the gain of the reverse stage is zero. The circuit consists of only transistors and resistors and so can be formed as an integrated circuit. By proper selection of the resistors in the circuit, the zero of the compensation circuit can be chosen to correspond to the frequency of the pole of the uncompensated input, so as to increase the bandwidth. Multiple reverse gain stages can be included, with a selected reverse gain stage switched into connection with the first stage, so as to provide a constant frequency response for different frequency response inputs.