发明公开
- 专利标题： Code converter and encoder including the same
- 专利标题（中）： 代码转换器和编码器包括它们
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申请号： EP89303273.0申请日： 1989-04-03
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公开(公告)号： EP0336681A3公开(公告)日： 1992-08-26
- 发明人: Abe, Masato , Asami, Fumitaka
- 申请人： FUJITSU LIMITED
- 申请人地址： 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 JP
- 专利权人： FUJITSU LIMITED
- 当前专利权人： FUJITSU LIMITED
- 当前专利权人地址： 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 JP
- 代理机构： Stebbing, Timothy Charles
- 优先权： JP82748/88 19880404
- 主分类号： H03M7/04
- IPC分类号： H03M7/04 ; H03M1/00 ; G06F7/544 ; H03M5/18 ; H04N9/79
摘要：
A code converter includes:
extraction means (31) for extracting a reference level from a binary-coded input signal, which is offset at the predetermined voltage level and varies arbitrarily with the same polarity as the voltage level; twos-complement conversion means(32), connected to the extraction means (31),for converting the reference level into a twos-complement value; and creation means (33), connected to said extraction means (31) and twos-complement conversion means(32) for adding an output signal of the twos-complement conversion means (32) and the binary-coded input signal, thereby producing a bipolar binary-coded output signal to which a polarity bit is added.
extraction means (31) for extracting a reference level from a binary-coded input signal, which is offset at the predetermined voltage level and varies arbitrarily with the same polarity as the voltage level; twos-complement conversion means(32), connected to the extraction means (31),for converting the reference level into a twos-complement value; and creation means (33), connected to said extraction means (31) and twos-complement conversion means(32) for adding an output signal of the twos-complement conversion means (32) and the binary-coded input signal, thereby producing a bipolar binary-coded output signal to which a polarity bit is added.
公开/授权文献
- EP0336681B1 Code converter and encoder including the same 公开/授权日：1996-12-04
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